The present invention relates to semiconductor memory devices, and more specifically, to a flash memory device, in which it can prevent the reliability of an erase operation from being lowered due to a leakage current in an erase operation on a block basis, and a method of controlling an erase operation of the same.
Generally, flash memory devices can be classified into a NOR type, which is generally used to store a small quantity of information at high speed, and a NAND type, which is generally used to store a great amount of information. The flash memory device performs a read operation, a program operation and an erase operation. The terms “program operation” and “erase operation” refer to operations relating to data storage in one or more memory cells by injecting/removing electrons into/from the floating gates. For example, in the program operation, only selected ones of a plurality of memory cells included in a memory cell block are programmed. The erase operation of the flash memory device is executed as electrons existing in the floating gate of the memory cell are discharged toward the P-well by means of FN tunneling. In the erase operation, data stored in the entire memory cells included in the memory cell block are erased at the same time. That is, the erase operation is performed on the basis of a memory cell block.
FIG. 1 is a circuit diagram of memory cells and pass gates for explaining the erase operation of a conventional flash memory device. In an erase operation, a bias voltage Vb of 0V is applied to a global word line GWL, and a bulk voltage VBK1 of 20V is applied to P-wells of memory cells CA1 to CAn and CB1 to CBn (where n is an integer). Sources and drains of the memory cells CA1 to CAn and CB1 to CBn are floated. In addition, to a gate of a NMOS transistor NM1 connected between a local word line WL1 of a memory cell block A, which is selected (i.e., which will be erased), and to the global word line GWL is applied a block select signal BKSEL1 of a voltage (Vcc) level. To a substrate (not shown) of the NMOS transistor NM1 is applied a bulk voltage VBK2 of 0V. The NMOS transistor NM1 is turned on in response to the block select signal BKSEL1, and the local word line WL1 is connected to the global word line GWL. As a result, a voltage of the local word line WL1 becomes 0V, and a voltage difference of 20V is generated between control gates (not shown) of the memory cells CA1 to CAn connected to the local word line WL1 and the P-wells of the memory cells CA1 to CAn. Accordingly, as electrons of the floating gates of the memory cells CA1 to CAn are discharged toward the P-wells, the erase operation of the memory cell block A is performed.
Meanwhile, a gate of an NMOS transistor NM2 connected between a local word line WL2 of a memory cell block B, which is not selected (i.e., which will not be erased), and the global word line GWL is applied with a block select signal BKSEL2 of 0V. In addition, to a substrate of the NMOS transistor NM2 is applied a bulk voltage VBK2 of 0V. The NMOS transistor NM2 is turned off in response to the block select signal BKSEL2, and the local word line WL2 is separated from the global word line GWL. This floats the local word line WL2 floated. Thereafter, the bulk voltage VBK1 of 20V, which is applied to the P-wells of the memory cells CB1 to CBn, is applied to the local word line WL2 by means of a capacitive coupling phenomenon, and a voltage level of the local word line WL2 is boosted to about 19V accordingly. This results in a voltage difference of 1 V between the local word line WL2 and the P-wells of the memory cells CB1 to CBn that is not sufficient to discharge electrons from the floating gates of the memory cells CB1 to CBn. As a result, while the erase operation is performed on the memory cell block A, the erase operation is not performed on the memory cell block B.
Although the NMOS transistor NM2 is turned off, the leakage current can be generated in the NMOS transistor NM2. Accordingly, the voltage level of the local word line WL2, which is boosted to the voltage level close to the bulk voltage VBK1, can gradually decrease. This leads to an increase in the voltage difference between the control gates and the P-wells of the memory cells CB1 to CBn. Therefore, a shallow erase may result, i.e., a small amount of electrons may be discharged unintentionally from floating gates of memory cells CB1 to CBn. Erase disturbance, such as shallow erase, becomes more significant when the number of memory cell blocks included in a flash memory device increases. For example, whenever memory cell blocks perform an erase operation one by one, a shallow erase phenomenon is repeatedly generated in memory cells of memory cell blocks that should not be erased. Consequently, as the threshold voltages of corresponding memory cells gradually decrease, the read operation failure is likely to increase.
Furthermore, there occurs a fast program phenomenon in which as the number of an erase operation is increased, the threshold voltage rises above a target voltage at the time of a program operation, or a slow erase phenomenon in which the threshold voltage is not sufficiently lowered to a target voltage at the time of an erase operation. This will be described in more detail below with reference to FIG. 2.
FIG. 2 is a characteristic graph showing a slow erase characteristic and a fast program characteristic depending on the number of an erase operation in the prior art. Although the program or erase operation is performed under the same condition, the threshold voltage of a memory cell increases as the program or erase operation is carried out and eventually becomes higher than a target voltage. The increase in the threshold voltage results in the program operation being performed fast or the erase operation being performed slowly. This phenomenon occurs when a voltage difference between the word lines and the bulk at the time of the erase operation is high. In other words, the higher the voltage difference between the word lines and the bulk at the time of the erase operation, the more severe the fast program and slow erase phenomena.
FIG. 3 is a characteristic graph showing a slow erase characteristic and a fast program characteristic depending on the level of an erase voltage in the prior art. It can be seen that if the erase operation is performed when the voltage difference between the word lines and the bulk is high (high potential erase), the fast program phenomenon and the slow erase phenomenon are generated sharply, whereas if the erase operation is performed when the voltage difference between the word lines and the bulk is low (low potential erase), the fast program phenomenon and the slow erase phenomenon are generated more gradually.
To prevent the occurrence of the fast program phenomenon and the slow erase phenomenon as described above, the erase operation should be performed with the voltage difference between the word lines and the bulk being low. In this case, however, an erase operation time may be lengthened and the erase operation may be performed improperly. If the erase operation is performed improperly, corresponding blocks may be flagged as invalid blocks that are not to be used. This reduces the number of available blocks and decreases the data storage capacity.